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30314hk 20140226-s00002/o3013hk 20131021-s00002 /32713hkpc/80812hk/53012hk no.a2064-1/27 http://onsemi.com semiconductor components industries, llc, 2014 march, 2014 overview the lc72717pw is a data demodulation lsi for receiving fm multiplex broadcasts fo r mobile reception in the darc format. this lsi includes an on-chip bandpass filte r for extracting the darc signal from the fm baseband signal. it also supports itu-r reco mmended fm multiplex frame structures (methods a, a?, b, and c) and can implement a compact, multifunction darc reception system. the lc72717pw?s package, pin assignment and electrical characteristics are same as the lc72715pw (vics-lsi). functionally, the lc72717pw is a product that vics function is removed from the lc72715pw. the lc72717pw is also control- compatible with the lc72711lw. note that a contract with the nhk engineering system, inc. may be required to produce darc compatible products in case, please contact with the nhk engineering system, inc. functions ? adjustment-free 76khz scf bandpass filter ? supports all fm multiplex frame structures (methods a, a?, b and c) under cpu control. ? msk delay detection system based on a 1t delay. ? error correction function based on a 2t delay (in the msk detection stage) ? digital pll based clock regeneration function ? shift-register 1t and 2t delay circuits ? block and frame synchronization detection circuits ? functions for setting the number of allowable bic errors and the number of synchronization protection operations. ? error correction using (272, 190) codes ? built-in layer 4 crc code checking circuit ? on-chip frame memory and memory c ontrol circuit for vertical correction ? 7.2mhz crystal oscillator circuit ? two power saving modes: stnby and ec stop ? applications can use either a parallel cp u interface (dma) or a ccb serial interface. ? supply voltage: 2.7v to 3.6v ordering number : ena2064d cmos ic mobile fm multiplex broadcast (darc) receiver ic lc72717pw ? ccb is on semiconductor? ?s original format. all addresses are managed by on semiconductor? for this format. ? ccb is a registered trademark of semiconductor components industries, llc. ordering information see detailed ordering and shipping informa tion on page 27 of this data sheet. sqfp64(10x10)
lc72717pw no.a2064-2/27 specifications absolute maximum ratings at ta = 25 ? c, v ss = 0v parameter symbol conditions ratings unit maximum supply voltage v dd -0.3 to +4.0 v input voltage v in 1 a0/cl, a1/ce, a2 /di, rst, stnby (v dd is equal to 2.7v or more.) -0.3 to +5.6 v a0/cl, a1/ce, a2 /di, rst, stnby (v dd is less than 2.7v.) -0.3 to v dd +0.3 v v in 2 input pin other than v in 1 -0.3 to v dd +0.3 v output voltage v out output pin -0.3 to v dd +0.3 v output current i out 1 int, rdy, dreq, d0 to d15, do 0 to 2.0 ma i out 2 output pin other than i out 1 0 to 1.0 ma allowable output current (total) ittl total for all the output pins 10 ma allowable power dissipation pd max 200 mw operating temperature topr ta ? 85 ? c -40 to +85 ? c storage temperature tstg -55 to +125 ? c allowable operating ranges at ta = -40 ? c to +85 ? c, v ss = 0v parameter symbol pin name type conditions ratings unit min typ max supply voltage v dd 2.7 3.6 v input high-level voltage v ih 1 a0/cl, a1/ce, a2/di, rst, stnby schmitt 0.7v dd 5.5 v v ih 2 iocnt1, iocnt2, dack d0, d1, d2, d3, d4, d5, d6, d7 wr, rd, a3, cs schmitt 0.7v dd v dd v v ih 3 sp, buswd, tin, tpc1, tpc2, tosel1, tosel2 0.7v dd v dd v input low-level voltage v il 1 a0/cl, a1/ce, a2/di, rst, stnby schmitt 0.0 0.3v dd v v il 2 iocnt1, iocnt2, dack d0, d1, d2, d3, d4, d5, d6, d7 wr, rd, a3, cs schmitt 0.0 0.3v dd v v il 3 sp, buswd, tin, tpc1, tpc2, tosel1, tosel2 0.0 0.3v dd v oscillation frequency fosc xin, xout oscillation circuit within ? 250ppm 7.2 mhz xin input sensitivity vxi xin capacitive coupling 400 mvrms input amplitude vmpx1 mpxin scf 100% demodulation composite v dd =3.3v 120 500 mvrms vmpx2 mpxin scf 100% demodulation composite v dd =2.7v 120 450 mvrms stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device functionality should n ot be assumed, damage may occur and reliability may be affected. functional operation above the stresses listed in the recommended operating ranges is not implied. extended exposure to stresses beyond the recomme nded operating ranges limits may affect device r eliab ility.
lc72717pw no.a2064-3/27 electrical characteristics at ta = -40 ? c to +85 ? c, v dd = 2.7v to 3.6v, v ss = 0v parameter symbol pin name type conditions ratings unit min typ max input high-level current i ih 1 a0/cl, a1/ce, a2/di, rst, stnby schmitt 1.0 ? a i ih 2 iocnt1, iocnt2, dack d0, d1, d2, d3, d4, d5, d6, d7 wr, rd, a3, cs schmitt 1.0 ? a i ih 3 sp, buswd, tin, tpc1, tpc2, tosel1, tosel2 1.0 ? a input low-level current i il 1 a0/cl, a1/ce, a2/di, rst, stnby schmitt -1.0 ? a i il 2 iocnt1, iocnt2, dack d0, d1, d2, d3, d4, d5, d6, d7 wr, rd, a3, cs schmitt -1.0 ? a i il 3 sp, buswd, tin, tpc1, tpc2, tosel1, tosel2 -1.0 ? a output high-level voltage v oh 1 clk16, data, flock, block, fck, bck, crc4 cmos i oh =-1ma v dd -0.4 v v oh 2 dreq, rdy, d0, d1, d2, d3, d4, d5, d6, d7, d8, d9, d10, d11, d12, d13, d14, d15, int cmos i oh =-2ma v dd -0.4 v output low-level voltage v ol 1 clk16, data, flock, block, fck, bck, crc4 cmos i ol =1ma 0.4 v v ol 2 dreq, rdy, d0, d1, d2, d3, d4, d5, d6, d7, d8, d9, d10, d11, d12, d13, d14, d15, int cmos i ol =2ma 0.4 v v ol 3 do nch-open drain i ol =2ma 0.4 v output leakage current ioff do v o =v dd 1.0 ? a hysteresis voltage vhys a0/c l, a1/ce, a2/di, rst, stnby, iocnt1, iocnt2, dack d0, d1, d2, d3, d4, d5, d6, d7 wr, rd, a3, cs 0.1v dd v internal feedback resistance rf xin, xout 1.0 m ? current drain i dd 6 12 ma bandpass filter characteristics at ta = 25 ? c, v dd = 2.7v to 3.6v, v ss = 0v parameter symbol conditions ratings unit min typ max input resistance rmpx 50 k ? reference supply voltage output vref vref, vdda=3v 1.5 v bpf center frequency fc flout 76.0 khz -3db band width fbw flout 19.0 khz group-delay in band width dgd flout ? 7.5 ? s gain gain flout-mpxin, f=76khz 20 db attenuation characteristic att1 flout, f=50khz 25 db att2 flout, f=100khz 15 db att3 flout, f=30khz 50 db att4 flout, f=150khz 50 db product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product per formance may not be indicated by the electrical characteristics if operated under different conditions.
lc72717pw no.a2064-4/27 buswd sp rst stnby cs a3 a2/di a1/ce a0/cl rd wr do vssd vddd int block diagram vssa vre f mpxin vdda flout cin vssd xin xout vddd iocnt1 iocnt2 clk16 data flock block fck bck crc4 dreq dack vssd vddd rdy d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 anti- aliasing filter 76khz bpf(scf) reference voltage divider 2t delay 1t delay lpf msk correction circuit lpf pn demodulation + - vref parallel if ccb if frame memory error correction and layer 2 crc timing control internal clock output control and cpu register clock regeneration synchronization regeneration layer 4 crc
lc72717pw no.a2064-5/27 package dimensions unit : mm spqfp64 10x10 / sqfp64 case 131ak issue a xxxxx = specific device code y = year m = month ddd = additional traceability data generic marking diagram* *this information is generic. please refer to device data sheet for actual part marking. xxxxxxxx ymddd xxxxx = specific device code y = year dd = additional traceability data xxxxxxxx ydd 10.0 0.1 12 0.5 (1.25) 0.10 10.0 0.1 12.0 0.2 12.0 0.2 64 0.18 +0.08 ? 0.03 0.10 1.7 max (1.5) 0.1 0.1 0 to10 0.5 0.2 0.15 0.05 (unit: mm) 11.40 11.40 0.28 0.50 1.00 soldering footprint* note: the measurements are not to guarantee but for reference only. *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d.
lc72717pw no.a2064-6/27 pin assignment list of pin functions pin no. name of pin io form state with rst=?l? description of functions 1 xout o oscillation pin for system clock (crystal oscillator) 2 vddd - - digital power pin 3 iocnt1 i input data bus i/o control 1 input pin (parallel if) * connect to vssd when ccb if (sp=h) is to be used. 4 iocnt2 i input data bus i/o control 2 input pin (parallel if) * connect to vssd when ccb if (sp=h) is to be used. 5 clk16 o l clock regeneration monitor pin 6 data o l demodulation data monitor pin 7 flock o l frame synchronization flag output pin (h: synchronized) 8 block o l block synchronization flag output pin (h: synchronized) 9 fck o l frame start signal output pin 10 bck o l block start signal output pin 11 crc4 o h layer 4 crc check result output pin 12 dreq o h dma req signal output pin (parallel if) 13 dack i input dma ack signal input pin (parallel if) * connect to vddd when ccb if (sp=h) is to be used. 14 vssd - - digital gnd pin 15 vddd - - digital power pin 16 rdy o h read data ready signal out put pin (parallel if) continued on next page. top view buswd sp rst stnby cs a3 a2/di a1/ce a0/cl rd wr nc do vssd vddd int 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 tin nc vssa vref mpxin vdda flout cin nc tpc1 tpc2 test tosel1 tosel2 vssd xin lc72717pw d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 xout vddd iocnt1 iocnt2 clk16 data flock block fck bck crc4 dreq dack vssd vddd rdy
lc72717pw no.a2064-7/27 continued from preceding page. pin no. name of pin io form state with rst=?l? description of functions 17 d0 i/o input data bus 0 to 7 i/o pins (parallel if) bus width switched to 8 bits or 16 bi ts according to the buswd setting * connect to vssd when ccb if (sp=h) is to be used. 18 d1 i/o input 19 d2 i/o input 20 d3 i/o input 21 d4 i/o input 22 d5 i/o input 23 d6 i/o input 24 d7 i/o input 25 d8 o hi-z data bus 8 to 15 output pins (parallel if) * output off for 8 bit bus width (buswd=l) 26 d9 o hi-z 27 d10 o hi-z 28 d11 o hi-z 29 d12 o hi-z 30 d13 o hi-z 31 d14 o hi-z 32 d15 o hi-z 33 int o h interrupt output pin for external cpu 34 vddd - - digital power pin 35 vssd - - digital gnd pin 36 o d o hi-z(h) o d output pin (ccb if) 37 nc - - nc pin (this pin must be open.) 38 wr i input write control signal input pin (parallel if) * connect to vddd when ccb if (sp=h) is to be used. 39 rd i input read control signal input pin (parallel if) * connect to vddd when ccb if (sp=h) is to be used. 40 a0/cl i input cl input pin (ccb if)/ address input pin 0 (parallel if) 41 a1/ce i input ce input pin (ccb if)/ address input pin 1 (parallel if) 42 a2/di i input di input pin (ccb if)/ address input pin 2 (parallel if) 43 a3 i input address input pin 3 (parallel if) * connect to vssd when ccb if (sp=h) is to be used. 44 cs i input chip selector input pin (parallel if) * connect to vddd when ccb if (sp=h) is to be used. 45 stnby i input standby mode input pin (h: standby) 46 rst i input system reset input pin (l: reset) 47 sp i input ccb/parallel setting input pin (h: ccb, l: parallel) 48 buswd i input data bus width setting input pin (l: 8 bits, h: 16 bits) 49 tin i input test input pin (this pin must be connected to vssd.) 50 nc - - nc pin (this pin must be open.) 51 vssa - - analog gnd pin 52 vref ao vdda/2 reference voltage output pin (vdda/2) 53 mpxin ai input baseband (multiplex) signal input pin 54 vdda - - analog power pin 55 flout ao vdda/2 subcarrier output pin (76khz bpf output) 56 cin ai input subcarrier input pin (comparator input) 57 nc - - nc pin (this pin must be open.) 58 tpc1 i input test input pin (this pin must be connected to vssd.) 59 tpc2 i input test input pin (this pin must be connected to vssd.) 60 test i input test mode setting pin (this pin must be connected to vssd.) 61 tosel1 i input test input pin (this pin must be connected to vssd.) 62 tosel2 i input test input pin (this pin must be connected to vssd.) 63 vssd - - digital gnd pin 64 xin i oscillation system clock pin (crystal oscillator/external clock input)
lc72717pw no.a2064-8/27 internal equivalent ci rcuit of analog pins name of pin pin number in parentheses internal equivalent circuit mpxin(53) flout(55) cin(56) vref(52) + - + - vref vdda vssa
lc72717pw no.a2064-9/27 cpu interface ccb (computer control bus), which is the sanyo original seri al bus format for sanyo?s aco ustic lsis, performs data input and output. the ccb address is transmitted with ce= ?l?, acknow ledging the ccb i/o mode when ce is set to ?h?. (1) list of ccb modes ccb address i/o mode description hexadecimal b0 b1 b2 b3 a0 a1 a2 a3 fah 0 1 0 1 1 1 1 1 input 16-bit control data input fbh 1 1 0 1 1 1 1 1 output output of data corresponding to the input clock (cl) portion fch 0 0 1 1 1 1 1 1 input layer 4 crc check circuit data input (on the 8-bit units) fad 1 0 1 1 1 1 1 1 output output of the register only (2) data input (ccb address fah) this is to set data to the lsi internal register. di in put includes both ccb address fah and 16-bit data (di0 to di15) are input. assignment of each bit is as shown in th e table below. though di12 to di15 ar e invalid data, it is necessary to enter the arbitrary data so that the total of 16 bits can be obtained. for the cont ents of each register and register address, refer to the chapter of cpu registers. (note that writing into the layer 4 crc check register w ill be described later (for the ccb address, use fch.)) (3) output of the corrected data (ccb address fbh) the corrected packet data is output from ls i. the ccb address, fbh, is input in di. the valid data to be output is maximum 288 bits. if the clock input (cl input) is interrupted halfway to set ce to the ?l? level, data output is not troubled by the next interrupt. ? the maximum data to be output is 288 bits (36 bytes) and the leading two bytes, to which the status register (stat) contents and the block number register (blno) contents are added, are output. ? stat and blno, which are the register contents outputs, are output respectively with lsb first. ? the corrected data is output sequentially beginnin g with the leading bit in data of one block. ? the bic code is not output. ? in case of data reading for multiple times by one interrupt signal (int), the output data is not guaranteed. stat (8) bln0 (8) data block (176) error-corrected data layer 2 crc (14) parity (82) 7 o d to 0 o d 15 o d to 8 o d 16 o d to 191 o d 205 o d to 192 o d 287 o d to 206 o d (lsb) input data (8-bit) (msb) register address invalid data di0 di1 di2 di3 di4 di5 di6 di7 di 8 di9 di10 di11 di12 to di15 bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit0 bit1 bit2 bit3 bit4 to bit7 di0 b0 b1 b2 b3 a0 a1 a2 a3 di1 di13 di14 di15 tch tcl ce cl di internal data latch tsu thd tel tes tlc teh
lc72717pw no.a2064-10/27 (4) layer 4 crc check circuit (ccb address fch) this is a function to detect the error in the data gr oup (layer 4 crc), transmitting the data group of specified number of bytes, via the ccb interface, to lsi. the ccb addre ss is fch. in this case, it is not necessary to send register address. the length of data group to be transmitted is on the 8-bit uni ts. here is not any upper limit (such as n pieces in the figure below) for the length of data to be transmitted at a time and data transmission can be divided into multiple times. (5) register output (ccb address fad) this is the dedicated register that can read only the status register (stat) and block number register (blno) in lsi. to di, the ccb address (fad) is input. data is output in order of the status register and the block number register. do do0 b0 b1 b2 b3 a0 a1 a2 a3 do1 d o 285 d o 286 tch tcl ce cl di tsu thd tel tes d o 287 do2 tddo teh tddo2 ce cl di b0 b1 b2 b3 a0 a1 a2 a3 cr1 n-3 n-2 n-1 tch tcl crc4 pin output tsu thd tel tes teh tcrc output after transmission of n pieces note: the number of ns must be on the 8-bit units. cr0 ce cl di do st0 b0 b1 b2 b3 a0 a1 a2 a3 st1 bln5 bln6 tch tcl tsu thd tel tes bln7 st2 tddo teh tddo2
lc72717pw no.a2064-11/27 symbol parameter min typ max unit tcl clock ?l? level time 0.7 ? s tch clock ?h? level time 0.7 ? s tsu data setup time 0.7 ? s thd data hold time 0.7 ? s tel ce wait time 0.7 ? s tes ce setup time 0.7 ? s teh ce hold time 0.7 ? s tlc data latch change time 0.7 ? s tddo*1 do data output time 135 320 ns tddo2 do data output off time 135 ns tcrc crc4 change period 0.7 ? s * 1 do data output change time from the ?h? level to the ?l ? level. output change time from the ?l? level to the ?h? level is determined by the external pull-up resistance value and load capacitance value. cpu interface this lsi can perform control via the parallel interface, in a ddition to the ccb interface. to use the parallel interface, it is necessary to set the sp pin = l. the data bus width can be selected with the buswd pin. (buswd pin - l: 8 bits, h: 16 bits) the dma transmission method can al so be selected according to th e setting of control register. (1) data input (register setting) data is set to the register in lsi. fo r accessing, input the register address to a0 to a3 pins and the write data to the d(n) pin. set the cs pin = l, and then the wr pin = l. subsequently, by setting the wr pin = h and the cs pin = h after the twwrl period, the data can be set to the register. it is ne cessary to keep an interval of tcywr or more before the next data input. tsawr twdh twwrl tcywr a0 to a3 cs wr d(n) thawr twds
lc72717pw no.a2064-12/27 (2) register output this is to read data from the register in lsi. only the status register (stat) and block number register (blno) in lsi can be read. for accessing, input the register address in a0 to a3, set the cs pin = l, and then the rd pin = l. this causes the rdy pin to change from ?h? to ?l?. then, data is output from the d(n) pin after the rdy pin becomes ?h?. it is necessary to keep an interval of tcyrd or more before the next data output. (n: 0-7 for buswd=l and 0 ? 15 for buswd=h.) by setting bit 3 (rdy) = 1 of the control register 2, the rdy pin output method can be changed. in this case, the rdy pin changes from ?h? to ?l? in the timing enabling output of the acquired data and the pin returns to ?h? after the end of data output (shown as timing 2 in the figure). tsard thard tdrdy2 twrdl tcyrd a0 to a3 cs rd d(n) valid output rdy (timing1: default) twrdy tdrdy rdy (timing2) tddatn trdh tdrdy+twrdy tdaton
lc72717pw no.a2064-13/27 (3) corrected data output this is to output the packet data after correction processing from lsi. the total length of output data is 176 bits (22 bytes) only, and the layer 2 crc data (14 bits) and parity da ta (82 bits) are not output. the corrected data is output, on either the 8-bit or 16-bit units, sequentially from the leading data among those in one packet. the bic code is not output. the accessing method is the same as for th e register output and the address ?0? is input to a0 to a3 pins. since this is different from the register output in the timing conditions during access, the timing chart is shown here separately from the register output. the rdy signal output method can also be selected similarly. data block (176 bits) data after error correction layer 2 crc (14 bits) parity (82 bits) structure of a single data packet (tot al length 272 bits: bic not included) (4) layer 4 crc check output this is a function to detect error of data group (layer 4 crc). the crc4 pin = ?h? or bit1 (crc4) = 1 of the status register after writing of the data group into the layer 4 crc register means that there is no error. the accessing method is the same as for the data input when setting up an internal register, and the address ?6h? of the layer 4 crc register is input into the register address. note: wr cycle wait for writing in layer 4crc register differs from the time of the data input of other register setup. (5) dma transmission output setting bit0 (dma) = 1 of control register 2 causes the dma mode, allowing the corrected data to be output in the dma method. for accessing, input the address ?0h? to a0 to a3 pins afte r falling of the dreq output pin, setting the cs pin = l, and then the rd pin = l. after the dreq pin = h, data is acquired from the d(n) pin. th en, the wait state occurs for the tcydm period or longer till the dreq pin becomes ?l?. in the dma mode, only 8 bits can be selected for the data bus width. (n: 0 to 7 for buswd=l. do not set buswd=h because it may cause fault.) the dack pin can be used instead of the rd pin for dma transmission. in this case, it is necessary to set bit1 (dma_rd) = 1 of the control register 2. it is also possible to change the polarity of dreq and dack pins. in this case, it is necessary to set bit4 (dreq) = 1 and bit5 (dack) = 1 of the control register 2. tsard thard trdh twdrd tcyrd a0 to a3 cs rd d(n) valid output rdy (timing1: default) twdrdy tdrdy rdy (timing2) valid output tddatn * a0 to a3 should be set to 0 during reading of corrected data. tdrdy2 tdaton tdrdy+twrdy
lc72717pw no.a2064-14/27 symbol parameter min typ max unit tsard address and cs to rd setup 20 ns thard *1 rd to address and cs hold 0 ns twrdl rd ?l? level width 340 ns tcyrd rd cycle wait 150 ns twrdy rdy width (at register output) 60 210 ns trdh rd data hold 0 40 ns tsawr address and cs to wr setup 20 ns thawr wr to address and cs hold 20 ns tcywr wr cycle wait 150 ns wr cycle wait(when writing data in layer 4crc register) 1200 ns twwrl wr ?l? level width 200 ns twds wr data setup 0 ns twdh wr data hold 20 ns tdrdy rdy output delay 0 40 ns tdrdy2 rdy output delay 2 0 40 ns twdrd rd width at output of corrected data buswd=l (8bit) 340 ns rd width at output of corrected data buswd=h (16bit) 620 ns twdrdy rdy width at output of corrected data buswd=l (8bit) 60 210 ns rdy width at output of corrected data buswd=h (16bit) 300 490 ns trddm dma start time 20 ns tdreq dack to dreq delay 260 ns tdaton datn output start time 0 40 ns tddatn datn output delay 0 40 ns tcydm dma cycle wait 420 ns twrdm rd ?l? level width at dma transmission output 300 ns * 1 specified up to the earliest negating of a0 to a3 and cs tdreq tcydm trdh dack (when dack is selected) rd (default) d(n) dreq twrdm a0 to a3 cs valid output tddatn trddm tsard thard valid output 0 0 *a0 to a3 should be set to 0 during dma transmission
lc72717pw no.a2064-15/27 cpu registers this lsi has both write registers and read registers. access to the registers is ma de via ccb if or parallel if. switching of access mode is made with the sp pi n. (ccb if: sp=h, parallel if: sp=l) (1) write registers setting any data to ?0h? or ?7h? or larger address of write-registers is prohibited. do not set any data to these addresses. ? list of write registers adr r/w register name description 0h - - reserved (setting prohibited) 1h w bic allowable number of bic errors 2h w syncb block synchronization: error protection count 3h w syncf frame synchronization: error protection count 4h w ctl1 control register 1 5h w ctl2 control register 2 6h w crc4 layer 4 crc register (for the parallel if only. ccb to use the dedicated address) 7h and beyond - - reserved (setting prohibited) ? 1h : number of allowa ble bic errors register to set the allowable number of bic er ror bits for determination of synchronization adr register name bit name description reset 1h bic 7-4 bic_f forward protection value (initial value 2) sets the allowable number of bic error bits (when synchronized). 0010b 3-0 bic_b backward protection value (initial value 2) sets the number of allowable bic error bits (when not synchronized). 0010b when the block synchronization determination output (block) is to be used determination of whether or not there is any fm multiplex data, it is recommended to set the allowabl e number of bic errors during backward protection to ?0001b? or ?0000b?. ? 2h : block synchronization: error protection count register to set the number of block synchronization protections for determination of block synchronization. adr register name bit name description reset 2h syncb 7-4 syncb_b backward protection value (register initial value 1: number of backward protections 2) number of backward protections = backward protection value +1 0001b 3-0 syncb_f forward protection value (register initial value 7: number of forward protections 8) number of forward protections = forward protection value +1 0111b to change the set value, it is necessary to set the valu e determined by deducting 1 from the desired number of protections.
lc72717pw no.a2064-16/27 the number of forward and backward protections can be set separately. the conditions for counting the number of protections are as follows: ? number of backward protections (not synchronized): block=l) when the timing of the free-ru n counter for lsi internal synchronization agrees with that of received bic, the protection counter is incremented by 1. similarly, when the timing between th e lsi internal counter and the received bic is lost, the protection counter is cleared to zero. th e count timing is the timing of the lsi internal counter. ? number of forward protections (synchronized: block=h) contrarily to the case of backward protection, the number of protections is counted up when the timing of lsi internal free-run counter is deviated from the received bic detectio n timing. the number of prot ections is cleared to zero when they agree. the figure below shows the agreement/d isagreement between the lsi internal timing and received bic timing and the relationship between the protection counter value and block signal. for the number of forward/backward protections of 3, the protection counter value at a timing of block signal changeover is 2, that is, smaller by 1. the number of protec tions is determined in the internal circuit by comparing the register set value for the number of forward/backward protections and the protection counter. accordingly, the register set value must be set to the value smaller than the desired number of protections by 1. for example, when the number of both forward and backward protections is 3 as shown below, it is necessary to set ?22h?. if the set value is ?00h?, the number of protections becomes 1 by definition for forward and backward protections. however, the operation becomes the same as fo r the state without the protection circuit. when the block synchronization flag output (block) is to be used for determination whether or not there is fm multiplex data, it is recommended to reset the value severer than the initial value. ? 3h : frame synchronization: error protection count register to set the number of frame synchronization protections for determination of frame synchronization adr register name bit name description reset 3h syncf 7-4 syncf_b backward protection value (register initial value 1: number of backward protections 2) number of backward protections = backward protection value +1 0001b 3-0 syncf_f forward protection value (register initial value 7: num ber of forward protections 8) number of forward protections = forward protection value +1 0111b to change the set value, it is necessary to set the valu e determined by deducting 1 from the desired number of protections. this lsi detects bic peculiar change points exis t at four points in one fra me and increases/decreases the counts of protection counter by determining agreement/disag reement with the timing counter for lsi internal frame synchronization. reset block bic position of synchronization counter received data for the register set value of 22h: the number of both the forward and backward protections become 3. protection counter bic 1 2 3 1 2 3 0 1 2 0 1 2 0 1 0
lc72717pw no.a2064-17/27 ? 4h : control register 1 register to control the block reset on/off, function activation/stop, and the data output method. adr register name bit name description reset 4h ctl1 7 crc4_rst layer 4 crc check circuit reset setting 1: reset on 0: reset off to cancel reset, it is necessary to set 0. 0 6 o d _move sets the o d pin output method changeover 0: hi-z state retained in states other than data output 1: changes in an interlock ed manner with the int signal *6 0 5 int_move sets changeover of co rrected data output method *4 0: outputs only data received at co mpletion of corre ction & layer 2 crc completion as well as during synchronization 1: outputs all of data 0 4 sync_rst synchronization regeneration circuit reset setting *1 1: reset on 0: reset off 0 to be set to cancel reset 0 3 ec_stop error correction function down setting *2 0: all functions activated 1: only msk detector circuit and synchronization regeneration circuit activated 0 2 vec_halt vertical error correction function down function *3 0: executes vertical error correcti on and second horizontal correction. 1: does not execute vertical error corr ection and second horizontal correction. 0 1 rtib real-time information block setting *5 0: real-time information blocks present. 1: no-real-time information block. 0 0 frame frame setting 0: specifies method b. 1: specifies method a. 0 * 1 with sync_rst=1, the synchronization status and the sync hronization protection status are cleared, resulting in the unsynchronized state. this function enables rapid pull-in of frame synchronization when the frame synchronization of new tuned and received data is deviat ed during tuning of a radio receiver. in this case, registers such as the number of allowable bic errors, the number of block forward/backward protections, and the number of frame forward/backward protections are not initialized. during rese t, the int signal is not output and the do pin becomes the hi-z output. * 2 with ec_stop=1, all of operations and data output related to error correction is shut down. msk demodulation, synchronization circuits, serial data input , and layer 4 crc circuit remain operative. * 3 with vec_halt=1 setting, all of lsi op eration related to vertical correction and second horizontal correction are shut down. only the data after first horizontal correction is output. * 4 since the output mode will be modified depending on the setting of the vec_out flag or the result of horizontal error correction, refer to the ?list of operation modes? section for detail. *5 in the itu-r recommended frame structure method a, a total of 12 data blocks can be inserted in the parity data area (the area that consists of 82 consecutive blocks of parity packets). if this ic is used ina system that has no real-time information blocks (rtib), this flag must be set. note that if this flag is changed, frame sync hronization is retained in the synchronized state for the time corresponding to the forward protection count, and then switc hes to the unsynchronized st ate. to quickly reestablish frame synchronization, applications must reset the synchronization circuit using the sync_rst flag. * 6 about the relationship between int and do, refer to the ?output format with do_move=1?section in the ?error correction? chapter.
lc72717pw no.a2064-18/27 ? 5h : control register 2 register to control the parallel if setting, vertically-corrected data output method, etc. adr register name bit name description reset 5h ctl2 7 reserved either keep an initial value or set it to 0. 0 6 blk_rst block synchronization circuit reset setting *1 1: reset on 0: reset off 0 to be set to cancel reset 0 5 dack dack signal polarity setting (effective for sp=l only) 0: negative logic for dack signal polarity 1: positive logic for dack signal polarity 0 4 dreq dreq signal polarity setting (effective for sp=l only) 0: negative logic for dreq signal polarity 1: positive logic for dreq signal polarity 0 3 rdy rdy signal timing setting (effective for sp=l only) 0: outputs the rdy signal in the timing 1. 1: outputs the rdy signal in the timing 2. 0 2 vec_out vertically error corrected data output method changeover setting *2 0: no vertically error corrected output if vertical error correction has not been made 1: all data output even when vertic al error correction has not been made 0 1 dma_rd dma read control signal selection setting (effective for sp=l only) 0: rd signal used 1: dack signal used 0 0 dma dma transmission function enable setting (effective for sp=l only) 0: dma transmission not used for reading of corrected data 1: dma transmission used for reading of corrected data 0 * 1 with blk_rst=1, the block synchronization state and block synchronization protection counter value are cleared. but this does not affect the functions related to frame synchronization. * 2 with vec_out=1, one frame of data completely free from er ror. the data similar to the horizontally-corrected data is output in the timing of output of ve rtically-corrected data even when ve rtical correction has not been made. ? 6h : layer 4 crc register register for data group writing to check the layer 4 crc. used on with the parallel if. the dedicated ccb address is to be used for ccb if. adr register name bit name description reset 6h crc4 7 crcdat7 layer 4 crc check data setting by writing value consecutively into this register, the layer 4 crc check of data group comprising multiple bytes can be made. the crc checked results can be known by c hecking the crc4 flag in the status register or crc4 pin output. 0 6 crcdat6 0 5 crcdat5 0 4 crcdat4 0 3 crcdat3 0 2 crcdat2 0 1 crcdat1 0 0 crcdat0 0
lc72717pw no.a2064-19/27 (2) read registers ? list of read registers adr r/w register name description 0h r pdato input this address into a0 to a3 after reading of error-corrected data 1h r stat status register 2h r blno block number register 3h and beyond - - reserved parallel mode: to read registers, send addr ess shown in the list of read registers. ccb mode: to read registers, send assigned ccb address (fbh or fad). it is not necessary to send address shown in the list of read registers. ? 1h : status register register to confirm various states adr register name bit name description reset 1h stat 7 vh determination on ve rtically error corrected data 0: data for which only horizontal correction is performed 1: data for which vertical and second horiz ontal correction after horizontal correction are performed 0 6 blk block synchronization state 0: data that is received when block synchronization is not established 1: data that is received when bloc k synchronization is established 0 5 frm frame synchronization state 0: data that is received when frame synchronization is not established 1: data that is received when fram e synchronization is established 0 4 err error correction state 0: data whose correction is completed and for which error is not detected by the layer 2 crc check 1: data whose correction is impossible or fo r which error is detected by the layer 2 crc check. 0 3 pri determination of parity block 0: data that is estimated to be data bl ock by the frame synchronization circuit 1: data that is estimated to be parity bl ock by the frame synchronization circuit 0 2 head frame head determination 1: data that is estimated to be the frame head block by the frame synchronization circuit 0: data other than above 0 1 crc4 layer 4 crc check result 0: error in layer 4 crc check result 1: no error in layer 4 crc check result 1 0 rtib real-time information block state 1: indicates the data is a real-time informatio n block.(this bit is valid only in method a?.) 0: the others 0 the value in the ?reset? column is the readable value immediately after canceling the reset.
lc72717pw no.a2064-20/27 ? 2h : block number register register to confirm the output data block number adr register name bit name description reset 2h blno 7 bln7 indicates the block number or parity block number of output data data block number 0 to 189 parity block number 0 to 81 0 6 bln6 0 5 bln5 0 4 bln4 0 3 bln3 0 2 bln2 0 1 bln1 0 0 bln0 0 the value in the ?reset? column is the readable value immediately after canceling the reset. ? data renewal timing of read register the timing for rewriting of read register (stat, blno) da ta is the timing for changing of int from h to l. ? read procedure of corrected data normally, the status register is first read because of occu rrence of interrupt to check the condition of corrected output data that is output by the interrupt signal, determining whet her or not read is necessary. fo r example, read is not made till the next interrupt if the error correction result is ng and read is not necessary. for ccb if, data read is made at the ccb address, ?fbh?, and determination is made by means of the status information added by 16 bits to see if the subsequent data is to be read. when interrupting read, set the ce signal to ?l?. it is possible to read the register in a manner a synchronou s with the interrupt signal when int_move is set to ?1?. for example, to check the current receivi ng state, read the status register to check blk (data received during block synchronization) and frm (data received during frame synchroni zation). in this case, read data is more close to the current receiving state, when vh=0 (data subject to horizo ntal correction only) in formation is used. ? layer 4 crc check to perform layer 4 crc check, the data group to be checked is transmitted. after transmission, it is determined that the data group is free from error if th e crc4 pin becomes the h-level output or the status register crc4 (layer 4 crc check result) is ?1?. the crc4 pin or crc4 flag of status register is either ?h? or ?1? when all bits of check register in lsi are ?0?. to perform layer 4 crc check using this fu nction, it is necessary to initialize th e crc check register in lsi before transmission of one group of one data group. initializa tion is made by setting the crc4_rst (layer 4 crc check circuit reset) of control register to ?1?. subsequently, to transmit the layer 4 crc check data, set crc4_rst back to 0 to cancel reset. the generating polynomial of crc code is as follows: g(x) = x 16 + x 12 + x 5 + 1
lc72717pw no.a2064-21/27 error correction (1) error correction and output conditions of error-corrected data (in the default state) the received data is subject to error detection by the la yer 2 crc and error correction by the (272,190) code for each one block (272 bits). at the end of correction, preparation for transmission to cpu is made and the int signal is output. this is called ?horizontal correction?. in the default state, this int signal is output only when the output data concerned meets all of three conditions as follows: ? data whose error correction is completed and for which layer 2 crc detects no error ? data received during block and frame synchronizations ? data in the data packet *depending on the register mode setting, horizontally-corr ected data may be output regardless of conditions of ? to ? above. when horizontal correction cannot cover completely, correction by the product code is made frame by frame. for data that cannot be horizontally corrected, the second hori zontal correction is made. this series of operations is called ?vertical correction?. conditions for the data obtained from vertically-corrected output are as follows in the default state: ? data that cannot be corrected by hor izontal correction, but that has been completely corrected by the vertical correction ? data in the data packet accordingly, horizontally-corrected data is not output. packet data that cannot be corrected horizontally or vertically is not output. the parity packet data after vertical correction is not output either. vertical correction is applied to the w hole packet data that have been receive d during frame synchronization, and is executed when horizontal correction canno t correct all packet (block) data. ver tical correction is not made when the error-free data is received for one frame or when the received data is not synchr onous in flame sync hronization during reception. for the packet whose error ha s been corrected by horizontal correctio n and any error-free packet, vertical correction is not made to prevent faulty correction. in the default setting, the applicable ve rtically-corrected output is not output when vertical corr ection has not been made. * depending on the register mode setting, the vertically-corrected data may be output regardless of whether or not vertical correction is to be made.
lc72717pw no.a2064-22/27 (2) error-corrected data output timing (basic restrictions) data received by lsi is corrected error and written sequenti ally without any interruption into the output data buffer memory. since this data buffer memory has a capacity for one -block data, the corrected data before reading is over- written by the next data if data read is delayed. in cons equence, it is essential to re ad data according to the timing stipulations shown below. this lsi specifies the output timing for each of horizo ntally and vertically corr ected data as follows: ? upon completion of preparation for the output data, lsi lowers the int pin to ?l? as a request for transmission. ? data output has the period during which only horizontal data can be read and the period during which horizontal and vertical data are read accor ding to the time division. ? complete data transmission within about 8ms after int = ?l?. when only the horizontally-corrected data can be output, data transmission is possible for about 17ms. even when cpu is in the course of reading, the output buffer is overwritten by the next output data once the specified time period is expired. ? the data amount that can be read by one horizontal and vertical transmission request (int) is one block only. vertically-corrected data is output se quentially beginning with the first block after completion of vertical correction, but the data of parity block is not output. horizontal data output period horizontal data output period vertical data output period period during which data guarantee is impossible output of only horizontal data divided output for horizontal and vertical data 1ms 18ms 990 ? s 990 ? s int 1ms 9ms int
lc72717pw no.a2064-23/27 (3) horizontally-corrected data output timing (relationship with the received data) the timing relationship between the recei ved data and interrupt control signal (int) for horizontar y-corrected data output is shown. but the delay from the actual received si gnal caused by demodulation in the msk demodulation block is ignored. block synchronization is established by determining the bic code. data of the nth packet can be output during receiving of the next (n + 1) packet data. (4) vertically-corrected data output timing vertical correction is made when the data of one frame is stored in the memory, frame synchronization has been established, and when horizontal correctio n cannot correct all of packet data. ver tical correction start timing is the head of a frame. during receiving of the first to 28 th packets of the n-th frame, horizont al correction of each packet is made, transferring data to the cpu interface. using the idling time in this period, vertical correction of the previous (n-1)-th frame data is made. vertically-corrected data is output fo r the amount equivalent to 190 blocks se quentially beginning with reception of the 29 th packet (block), in such a manner that one block data is output each time one block is received. only data of data block in the fm multiplex broadcasting frame is output. the final 190 th block is output during reception of the 218 th block. in the vertically-corrected data output timing, the packet data corrected by vertical correction is not output (int not issued). however, vertical correction data output order is not shortened for the amount equivalent to the packet data that is not output. for example, if the first to 100 th data packets have been horizontally corrected, the 101 st vertically corrected packet data is output, not at the reception point of the block number 29 th , but at the 129 th packet data reception point. (n-1) packet n packet (n+1) packet received data (n-1) packet data output period period during which data cannot be guaranteed n packet data output period bic bic 18ms 300ns max 62.5 ? s 300ns max 1ms bck int 990 ? s data output period after vertical correction of previous frame reception block no. n-th frame (n-1)-th frame 271 272 1 2 3 28 29 30 31 218 219 220 18ms 1ms 12 189 190 bck fck int 18ms 9ms 9ms 18ms ? ?
lc72717pw no.a2064-24/27 (5) list of operation modes depending on the set value of int_move (bit 5 of control register 1) and vec_out (bit 2 of control register 2), the int signal output timing and output data are modified. in the table below, ? indicates ?output?, ? indicates ?no output.? and - indicates ?none applicable.? parameter int_move vec_out horizontal correction result horizontally-corrected output vertically-corrected output ok data ng data parity ok data ng data default value 0 0 ok ? - ? ? - ng ? ? ? ? *1 ? mode 1 1 1 ok ? - ? ? *2 - ng ? ? ? ? *2 ? mode 2 1 0 ok ? - ? ? *3 - ng ? ? ? ? *4 ? mode 3 0 1 ok ? - ? ? - ng ? ? ? ? ? * 1 only data whose horizontal correction result is ng an d whose vertical correction result is ok is output. * 2 all of vertically-corrected outputs (190 blocks/frame) are output, in both cases of horizontal correction result of ok and ng, regardless of whether the verti cal correction result is ok or ng. * 3 the vertically-corrected data is not output when there is no data that is determined to be ng because all the horizontal correcti on results are ok. * 4 when there is any data whose hori zontal correction result becomes ng, a ll of vertically-corrected outputs (190 blocks/frame) are output regardless of whether the vertical correction result is ok or ng. (6) output format with do_move=1 the relationship between int and do is shown below. do becomes ?l? in synchronous with the falling edge of int, and return to ?h? before 3ms or more against the next falling edge of int. therefore, when the data read is started while do is ?l?, there is margin time 3ms or more agains t the falling edge of int. this timing diagram is for the case when the data read is not performed. when the data read is performed, do returns to ?h? after completion of read. do (output of only horizontal data) 18ms horizontal data output period 990 ? s period during which data cannot be guaranteed 1ms int 3ms or more 9ms 990 ? s do (output of horizontal and vertical data) 1ms int 990 ? s horizontal data output period period during which data cannot be guaranteed vertical data output period 3ms or more 3ms or more
lc72717pw no.a2064-25/27 example of an applicat ion circuit diagram this is an application circuit example when the ccb serial in terface is selected, using a mi crocomputer operating on the supply voltage of 3v. the do pin must be pulled up by a resistor to the supply voltage. (1)this example of an application circuit is a circuit of reference, and does not guarantee the characteristic. (2)the capacitance value to be connected to the above crystal oscillator is the reference value. before use, confirm by crystal supplier that oscillation is free from trouble using the actual substrate. (3)a bypass capacitor needs to be connected near the power supply terminal. v dd fm composite lc72717pw tin nc vssa vref mpxin vdda flout cin nc tpc1 tpc2 test tosel1 tosel2 vssd xin 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 xout vddd iocnt1 iocnt2 clk16 data flock block fck bck crc4 dreq dack vssd vddd rdy 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 buswd sp rst stnby cs a3 a2/di a1/ce a0/cl rd wr nc do vssd vddd int 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 5.1k ? xtal 7.2mhz 560pf 3.3 ? f 10 ? f 22pf 22 p f 100 ? f 0.1 ? f gnd cpu interface 330pf 0.1 ? f 0.1 ? f 22 ? h 22 ? h 0.1 ? f 0.1 ? f
lc72717pw no.a2064-26/27 cautions operation at reset and standby (1) reset signal after crystal was oscillated and stabili zed, reset operation is performed by setting the rst pin input level to v il or less for 300ns or more at the supply voltage (v dd ) of 2.5v or more. (see the figure below). be sure to perform reset operation at power on. (2) pin state at reset refer to the list of pin functions. (3) reset operation range the reset signal causes reset inside lsi, causing return to the initial state. though the crystal oscillation circuit is not stopped, the internal divider circuit is stopped. (4) data input after reset if 300ns or more time has elapsed after completion of reset, th e register write control circuit is ready for activation. (5) standby mode set the stnby pin to the ?h? level, and lsi enters the st andby mode. in this mode, all of lsi operations can be stopped. after canceling of stnby, the time is requi red till the crystal oscillation circuit becomes stable. digital pin output states during standby is the same as for that dueing reset. on the other hand, analog output pins (flout, vref) are l outputs (vdda/2 is output during reset). similarly to the case of reset, the lsi inside is reset to return to the initial state. supply voltage rst 2.5v v ih v il (0.3v dd ) 300ns(min)
lc72717pw no.a2064-27/27 ordering information device package shipping (qty / packing) LC72717PW-H sqfp64(10x10) (pb-free / halogen free) 500 / tray foam lc72717pw-nh sqfp64(10x10) (pb-free / halogen free) 1000 / tape & reel *note the number of shipments of this lsi will be reported to nhk-es by our company. (the number of samples is excluded) ps ? the darc (data radio channel) fm mult iplex broadcast technology was developed by nhk (japan broadcasting corporation). ? the darc is a registered trademark of nhk engineering system, inc. (nhk-es). ? a separate contract with nhk-es is required in advance for the manufacture and/or sales of electronic equipment in japan and other countries that uses the patents, which are related to darc technology, and which are registered in japan and such other countries by nhk independently or in cooperation with a third party. ? darc and the logo shown on the right-hand side can be displayed on electronic equipment that uses darc technology by the conclusion of a contract with nhk-es. please contact nhk engineering sy stem, inc. for further details. contact information: nhk engineering system, inc. phone: +81- (0)3-5494-2400 (main) url: http://www.nes.or.jp/index.html on semiconductor and the on logo are registered trademarks of semiconductor components industries, llc (scillc). scillc owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. a listing of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent-marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc mak es no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability ar ising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequentia l or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s techn ical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorize d for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other appli cation in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of persona l injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture o fthe part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws a nd is not for resale in any manner.

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